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2m x 32 flash module elm road, west chirton industrial estate, north shields, ne29 8se, england. tel +44 (0191) 2930500. fax +44 (0191) 2590997 e-mail: hmpsales@mosaicsemi.com pin functions block diagram pin definition see page 2. package details plastic j leaded jedec plcc max. dimensions (mm) - 25.27 x 25.27 x 5.08 features ? access times of 90, 120 and 150ns. ? 5v + 10%. ? commercial and industrial temperature grades ? 68 j leaded jedec surface mount package. ? industry standard pinout. ? user configurable as 8/16/32 bits wide ? 64k byte sector size. ? operating power (32 bit) 1.32w (max) ? low power standby. (ttl) 22mw (max) ? completely static operation. ? 10,000 write and erase (w/e) cycles. ? 10 year data retention. puma 68f64006x - 90/12/15 issue 5.0 december 1999 description the puma 68f64006x is a 2m x 32 flash module housed in a 68 j leaded surface mount package with access times of 90, 120 and 150ns. the output width is user configurable as 8, 16 or 32 bits wide using 4 chip selects (/cs1~4) for optimum application flexibility. the module incorporates embedded algorithms for program and erase with sector architecture and supports full chip erase. the device also features hardware sector protection, which disables both program and erase operations in any of the 32 sectors on the module. the device is available to commercial and industrial temperature grades. description signal address input a0~a20 data input/output d0~d31 chip select /cs1~4 write enable /we output enable /oe hardware reset /reset no connect nc power v cc ground v ss /we /cs1 d16~23 d0~7 d8~15 d24~31 /cs2 /cs3 /cs4 a0~a20 2m x 8 flash /oe /reset 2m x 8 flash 2m x 8 flash 2m x 8 flash
issue 5.0 december 1999 page 2 pin definition - puma68f64006x pin signal pin signal 1 v cc 35 v cc 2 a19 36 a13 3 /cs1 37 a12 4 /cs2 38 a11 5 /cs3 39 a10 6 /cs4 40 a9 7 a17 41 a8 8 a18 42 a7 9 d16 43 d0 10 d17 44 d1 11 d18 45 d2 12 d19 46 d3 13 v ss 47 v ss 14 d20 48 d4 15 d21 49 d5 16 d22 50 d6 17 d23 51 d7 18 v cc 52 v cc 19 d24 53 d8 20 d25 54 d9 21 d26 55 d10 22 d27 56 d11 23 v ss 57 v ss 24 d28 58 d12 25 d29 59 d13 26 d30 60 d14 27 d31 61 d15 28 a6 62 a14 29 a5 63 a15 30 a4 64 a16 31 a3 65 /we 32 a2 66 /oe 33 a1 67 /reset 34 a0 68 a20
dc operating conditions issue 5.0 december 1999 page 3 parameter symbol test condition min typ max unit input leakage current address, /oe i li1 v cc =v cc max, v in =0v or v cc - - + 4 m a a9 input leakage current i li2 v cc =v cc max, a9=12.5v - - 200 m a other pins i li3 v cc =v cc max, v in =0v or v cc - - + 4 m a output leakage current i lo v cc =v cc max, v out =0v or v cc - - + 4 m a v cc operating current 32 bit i cco32 /cs (1) =v il ,/oe=v ih ,i out =0ma, f=6mhz - - 160 ma 16 bit i cco16 as above - - 82 ma 8 bit i cco8 as above - - 43 ma v cc program erase current 32 bit i ccp32 programming in progress - - 240 ma 16 bit i ccp16 as above - - 122 ma 8 bit i ccp8 as above - - 63 ma standby supply current ttl i sb1 v cc =v cc max,/cs=v ih (1) /oe=v ih - - 4 ma autoselect/sector protect voltage v id v cc =5.0v 11.5 - 12.5 v output voltage low v ol i ol =12ma, v cc = v cc min - - 0.45 v output voltage high v oh1 i oh =-2.5ma, v cc = v cc min 2.4 - - v low v cc lock-out voltage v lko 3.2 - 4.2 v absolute maximum ratings (1) recommended operating conditions notes : (1) minimum dc voltage on input or i/o pins is -0.5v. during voltage transitions, inputs may overshoot v ss to -2.0v for periods of up to 20ns . see maximum dc voltage on output and i/o pins is v cc +0.5v. during voltage transitions, outputs may overshoot to v cc +2.0v for periods up to 20ns. (2) minimum dc input voltage on a9, oe#, reset# pins is -0.5v. during voltage transitions, a9 ,oe# and reset# pins may overshootv ss to -2.0v for periods of up to 20ns. maximum dc input voltage on a9, oe# and reset# is 12.5v which may overshoot to 13.5v fo periods up to 20ns. (3) no more than one output shorted at a time. duration of a short circuit should not be greater than one second. stresses greater than those listed in this section may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this of this specification is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v input high voltage v ih 2.0 - v cc +0.5 v input low voltage v il -0.5 - 0.8 v operating temperature (commercial ) t a 0 - 70 o c (industrial) t ai -40 - 85 o c (i suffix) parameter symbol min typ max unit voltage on any pin relative to v ss v t -2.0 - +7.0 v supply voltage (2) -2.0 - +7.0 v voltage on a9 relative to v ss v a9 -2.0 - +12.5 v storage temperature t stg -65 - +125 o c dc electrical characteristics (v cc =5v +10%, t a =-40 o c to 85 o c) notes (1) /cs1~4 inputs operate simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for 8 bit mode.
issue 5.0 december 1999 page 4 166w 30pf i/o pin 1.76v capacitance (v cc = 5.0v, t a = 25 o c, f=1mhz.) test conditions output load ? input pulse levels : 0.45v to 2.40v ? input rise and fall times : 20ns ? input and output timing reference levels : 1.5v ? output load : see load diagram. ? module tested in 32 bit mode. ?v cc = 5v +10% note : these parameters are calculated not measured. parameter symbol test condition min typ max unit input capacitance ( address, /oe, /we) c in1 v in =0v - - 35 pf other pins c in2 v in =0v - - 17 pf output capacitance 32 bit mode c out v out =0v - - 40 pf
ac operating conditions issue 5.0 december 1999 page 5 90 120 150 parameter symbol min typ max min typ max min typ. max units write cycle time t wc 90 - - 120 - - 150 - - ns address setup time t as 0 - - 0 - - 0 - - ns address hold time t ah 45 - - 50 - - 50 - - ns data setup time t ds 45 - - 50 - - 50 - - ns data hold time t dh 0 - - 0 - - 0 - - ns read recover before write t ghwl 0 - - 0 - - 0 - - ns /cs setup time t cs 0 - - 0 - - 0 - - ns /cs hold time t ch 0 - - 0 - - 0 - - ns /we pulse width t wp 45 - - 50 - - 50 - - ns /we pulse width high t wph 20 - - 20 - - 20 - - ns programming operation (2) t whwh1 - 7 - - 7 - - 7 - m s sector erase operation (2) t whwh2 - - 8 - - 8 - - 8 s v cc setup time t vcs 50 - - 50 - - 50 - - m s 90 120 150 parameter symbol min max min max min max units read cycle time t rc 90 - 120 - 150 - ns address to output delay t acc - 90 - 120 - 150 ns chip select to output t cs - 90 - 120 - 150 ns output enable to output t oe - 40 - 50 - 55 ns output enable to output high z t df - 20 - 30 - 35 ns output hold from address /cs or /oe whichever occurs first t oh 0 - 0 - 0 - ns /reset pin low to read t ready - 20 - 20 - 20 m s read cycle erase/program notes : (1) this does not include the preprogramming time. (2) not 100% tested.
issue 5.0 december 1999 page 6 erase/program alternate /cs controlled writes notes : (1) this does not include the preprogramming time. (2) not 100% tested. 90 120 150 parameter symbol min typ max min typ max min typ. max units write cycle time t wc 90 - - 120 - - 150 - - ns address setup time t as 0 - - 0 - - 0 - - ns address hold time t ah 45 - - 50 - - 50 - - ns data setup time t ds 45 - - 50 - - 50 - - ns data hold time t dh 0 - - 0 - - 0 - - ns read recover before write t ghel 0 - - 0 - - 0 - - ns /cs setup time t ws 0 - - 0 - - 0 - - ns /cs hold time t wh 0 - - 0 - - 0 - - ns /we pulse width t cp 45 - - 50 - - 50 - - ns /we pulse width high t cph 20 - - 20 - - 20 - - ns programming operation (2) t whwh1 - 7 - - 7 - - 7 - m s sector erase operation (2) t whwh2 - - 8 - - 8 - - 8 s parameter jedec std description test setup all speed options unit t ready /reset pin low (not during embedded algorithms) to read or write* max 20 m s t rp /reset# pulse width min 500 ns t rh /reset# high time before read* min 50 ns hardware reset (/reset) *note : not 100% tested
timing waveforms issue 5.0 december 1999 page 7 addresses /cs# /oe data v cc 555h pa pa pa a0h status d out pro g ram command sequence (last two cycles) read status data (last two cycles) t wc t as t ah t ch t ghwl t wp t wph t whwh1 t vcs t cs t dh t ds /we pd addresses stable output valid addresses /cs# /oe /we outputs /reset hi g h z hi g h z t rc t acc t oe t oeh t cs t df t oh read operation timings program operation timings note : pa = program address, pd = program data, d out is the true data at the program address
issue 5.0 december 1999 page 8 chip/sector erase operation timings. data# polling timings (during embedded algorithms) addresses /cs# /oe data v cc 2aah sa va va 55h complete t wc t as t ah t ch t ghwl t wp t wph t whwh2 t vcs t cs t dh t ds /we 555h for chip erase in progress 30h 10 for chip erase note : sa=sector address. va=valid address for readin g status data. va va va complement complement true true valid data valid data status data status data addresses /cs# /oe /we d7 d0~d6 t rc t acc t ce t ch t oeh t oe t df t oh hi g h z hi g h z note : va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
issue 5.0 december 1999 page 9 addresses /cs# /oe /we d6/d2 va va va va t rc t acc t cs t ch t oeh t df t oh vs vs vs vd note : va=valid address; not required for d6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. vs=valid status, vd=valid data. (first read) (second read) (stops toggling) toggle bit timings (during embedded algorithms) temporary sector group timings /reset /cs# /we program or erase command sequence 0 to 5v 12v t vdir t vdir t rsp 0 to 5v
issue 5.0 december 1999 page 10 /cs, /oe /reset t rp /cs, /oe /reset t rh t rp t ready reset timings not during embedded algorithms reset timings during embedded algorithms alternate /cs# controlled write operation timings addresses /we /oe /cs# data /reset d7# d out pa data # pollin g 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase a0 for program 55 for erase pd for program 30 for sector erase 10 for chip erase t wc t as t wh t ghel t cp t ws t cph t ds t dh t rh t whwh1 or 2 notes: 1. pa =pro g ram address, pd=pro g ram data, sa=sector address, d7#=compliment of data input, d out =array data. 2. fi g ure indicates the last two bus cycles of the command sequence. t ah /reset timings
algorithms issue 5.0 december 1999 page 11 start write program command sequence data poll from system verify data last address increment address programming completed no no yes yes embedded program algorithm in progress note : see the appropriate command definitions table for program command sequence program operation erase operation start write erase command sequence data poll from system data =ffh? erasure completed no embedded erase algorithm in progress note : 1. see the appropriate command definitions table for erase command sequence. 2. see 'd3 : sector erase timer' for more information. yes
issue 5.0 december 1999 page 12 start /reset=v ih temporary sector group unprotect completed (note 2) perform erase or program operations /reset=v id (note 1) notes: 1. all protected sector groups unprotected. 2. all previously protected sector groups are protected once again. temporary sector group unprotect operation data# polling operation start read d7~d0 addr=va d7=data? d5=1? read d7~d0 addr = va no yes yes note : 1. va = valid address for programming. during a sector erase operartion, a valid adddress is an address within any sector selected for erasure. during chip erase, a valid address is any non-protected sector address. 2. d7 should be rechecked even if d5 = '1' beceause d7 may change simultaneously with d5. d7=data? fail pass yes no no
issue 5.0 december 1999 page 13 toggle bit algorithm start read d7~d0 to gg le bit = to gg le? d5=1? read d7~d0 twice no yes yes note : 1. read toggle bit twice to determine whether or not it is toggling. see text. 2. recheck toggle bit because it may stop toggling as d5 changes to '1' . see text. program/erase operation not complete, write reset command. yes no read d7~d0 to gg le bit = to gg le? program/erase operation complete (note 1.) (notes 1,2) no
device bus operations issue 5.0 december 1999 page 14 this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register it self does not occupy any addressable memory location.the register is composed of latches that store the commands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the appropriate device bus operations table lists the inputs and control levels required, and the resulting output. the following subsections describe each of these operations in further detail. requirements for reading array data to read array data from the outputs, the system must drive the /cs# and /oe pins to v il . /cs# is the power control and selects the device. /oe is the output control and gates array data to the output pins. /we should remain at v ih . the internal state machine is set for reading array data upon device power up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see reading array data for more information. refer to the ac read operations table for timing specifications and to the read operations timings diagram for the timing waveforms. i cco32 , i cco16 and i cco8 in the dc characteristics table represents the active current specification for reading array data. writing commands/command sequences to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive /we and /cs# to v il , and /oe to v ih . an erase operation can erase one sector, multiple sectors, or the entire device. the sector address tables indicate the address space that each sector occupies. a sector address consists of the address bits required to uniquely select a sector. see the command definitions section for details on erasing a sector or the entire chip, or suspending/resuming the erase operation. after the system writes the autoselect command sequence, the device enters the autoselect mode. the system can then read autoselect codes from the internal register (which is separate from the memory array) on d7~d0. standard read cycle timings apply in this mode. refer to the autoselect mode and autoselect command sequence sections for more information. i ccp32 , i ccp16 and i ccp8 in the dc characteristics table represents the active current specification for the write mode. the ac characteristics section contains timing specification tables and timing diagrams for write operations.
issue 5.0 december 1999 page 15 program and erase operation status during an erase or program operation, the system may check the status of the operation by reading the status bits on d7~d0. standard read cycle timings and i cco32 , i cco16 and i cco8 read specifications apply. refer to write operation status for more information, and to each ac characteristics section for timing diagrams. standby mode when the system is not reading or writing to the device,it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the /oe input. the device enters the cmos standby mode when /cs and /reset pins are both held at v cc 0.5 v. (note that this is a more restricted voltage range than v ih .) the device enters the ttl standby mode when /cs# and /reset pins are both held at v ih . the device requires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. the device also enters the standby mode when the /reset pin is driven low. refer to the next section, /reset: hardware reset pin. if the device is deselected during erasure or program-ming, the devi ce draws active current until the operation is completed. in the dc characteristics tables, i sb represents the standby current specification. /reset: hardware reset pin the /reset pin provides a hardware method of resetting the device to reading array data. when the system drives the /reset pin low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the /reset pulse. the device also resets the internal state ma-chine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of the reset# pulse. when /reset is held at v il , the device enters the ttl standby mode; if /reset is held at v ss 0.5 v, the device enters the cmos standby mode. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firm-ware from the flash memory. the system can read data t rh after the /reset pin returns to v ih . refer to the ac characteristics tables for /reset parameters and timing diagram.
issue 5.0 december 1999 page 16 output disable mode when the /oe input is at v ih , output from the device is disabled. the output pins are placed in the high impedance state. autoselect mode the autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on d7~d0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id (11.5 v to 12.5 v) on address pin a9. address pins a6, a1, and a0 must be as shown in autoselect codes (high voltage method) table. in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. refer to the corresponding sector address tables. the command definitions table shows the remaining address bits that are dont care. when all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on d7~d0. to access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in the command definitions table. this method does not require v id . see command definitions for details on using the autoselect mode. sector group protection/unprotection the hardware sector group protection feature disables both program and erase operations in any sector group. each sector group consists of four adjacent sectors. table 4 shows how the sectors are grouped, and the address range that each sector group contains. the hardware sector group unprotection feature re-enables both program and erase operations in previously protected sector groups. sector group protection/unprotection must be implemented using programming equipment. the procedure requires a high voltage (v id ) on address pin a9 and the control pins. the device is shipped with all sector groups unprotected. see autoselect mode for details. temporary sector group unprotect this feature allows temporary unprotection of previously protected sector groups to change data in-system. the sector group unprotect mode is activated by setting the /reset pin to v id . during this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. once v id is removed from the /reset pin, all the previously protected sector groups are protected again. figure 1 shows the algorithm, and the temporary sector group unprotect diagram shows the timing waveforms, for this feature.
issue 5.0 december 1999 page 17 hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to the command definitions table). in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse glitch protection noise pulses of less than 5 ns (typical) on /oe, /cs# or /we do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of /oe = v il , /cs# = v ih or /we = v ih .to initiate a write cycle, /cs# and /we must be a logical zero while /oe is a logical one. power-up write inhibit if /we = /cs# = v il and /oe = v ih during power up, the device does not accept commands on the rising edge of /we. the internal state machine is automatically reset to reading array data on power-up.
command definitions issue 5.0 december 1999 page 18 writing specific address and data commands or sequences into the command register initiates device operations. the command definitions table defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. all addresses are latched on the falling edge of /we or /cs#, whichever happens later. all data is latched on the rising edge of /we or /cs#, whichever happens first. refer to the appropriate timing diagrams in the ac characteristics section. reading array data the device is automatically set to reading array data after device power- up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase suspend mode. the system can read array data using the standard read timings,except that if it reads at an address within erase- suspended sectors, the device outputs status data.after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see erase suspend/erase resume commands for more information on this mode. the system must issue the reset command to re-enable the device for reading array data if d5 goes high, or while in the autoselect mode. see the reset command section, next. see also requirements for reading array data in the device bus operations section for more information. the read operations table provides the read parame-ters, and read operation timings diagram shows the timing diagram. reset command writing the reset command to the device resets the device to reading array data. address bits are dont care for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to reading array data (also applies to programming in erase suspend mode). once programming begins,however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during erase suspend). if d5 goes high during a program or erase operation, writing the reset command returns the device to read-ing array data (also applies during erase suspend).
issue 5.0 december 1999 page 19 autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. the command definitions table shows the address and data requirements. this method is an alternative to that shown in the autoselect codes (high voltage method) table, which is intended for prom programmers and requires v id on address bit a9. the autoselect command sequence is initiated bywriting two unlock cycles, followed by the autoselect command. the device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. a read cycle at address xx00h retrieves the manufacturer code. a read cycle at address xx01h returns the device code. a read cycle containing a sector address (sa) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. refer to the sector address tables for valid sector addresses. the system must write the reset command to exit the autoselect mode and return to reading array data. byte program command sequence programming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verify the programmed cell margin. the command definitions take shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. the system can determine the status of the program operation by using d7 or d6. see write operation status for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. note that a hardware reset immediately terminates the programming operation. the program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a 0 back to a 1. attempting to do so may halt the operation and set d5 to 1, or cause the data# polling algorithm to indicate the operation was successful. however, a succeeding read will show that the data is still 0. only erase operations can convert a 0 to a 1.
issue 5.0 december 1999 page 20 chip erase command sequence chip erase is a six-bus-cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. the command definitions table shows the address and data requirements for the chip erase command sequence. any commands written to the chip during the embedded erase algorithm are ignored. note that a hardware reset during the chip erase operation immediately terminates the operation. the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. the system can determine the status of the erase operation by using d7, d6 or d2. see write operation status for information on these status bits. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. figure 3 illustrates the algorithm for the erase operation. see the erase/ program operations tables in ac characteristics for parameters, and to the chip/sector erase operation timings for timing waveforms. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two un-lock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. the command definitions table shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram the memory prior to erase. the embedded erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of 50 s begins. during the time-out period, additional sector addresses and sector erase commands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise the last address and command might not be accepted, and erasure may begin. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. if the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor d3.
issue 5.0 december 1999 page 21 any command other than sector erase or erase suspend during the time-out period resets the device to reading array data. the system must rewrite the command sequence and any additional sector addresses and commands. the system can monitor d3 to determine if the sector erase timer has timed out. (see the d3: sector erase timer section.) the time-out begins from the rising edge of the final /we pulse in the command sequence. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. note that a hardware reset during the sector erase operation immediately terminates the operation. the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by using d7, d6 or d2. refer to write operation status for information on these status bits. figure 3 illustrates the algorithm for the erase operation. refer to the erase/program operations tables in the ac characteristics section for parameters, and to the sector erase operations timing diagram for timing waveforms. erase suspend/erase resume commands the erase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. writing the erase suspend command during the sector erase time-out immediately terminates the time-out period and suspends the erase operation. addresses are dont-cares when writing the erase suspend command. when the erase suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. however, when the erase suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (the device erase suspends all sectors selected for erasure.) normal read and write timings and command definitions apply. reading at any address within erase-suspended sectors produces status data on d7~d0. the system can use d7, or d6 and d2 together, to determine if a sector is actively erasing or is erase-suspended. see write operation status for information on these status bits.
issue 5.0 december 1999 page 22 after an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. the system can determine the status of the program operation using the d7 or d6 status bits, just as in the standard program operation. see write operation status for more information. the system may also write the autoselect command sequence when the device is in the erase suspend mode. the device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to the erase suspend mode, and is ready for another valid operation. see autoselect command sequence for more information. the system must write the erase resume command (address bits are dont care) to exit the erase suspend mode and continue the sector erase operation. further writes of the resume command are ignored. another erase suspend command can be written after the device has resumed erasing.
write operation status issue 5.0 december 1999 page 23 the device provides several bits to determine the status of a write operation: d2, d3, d5, d6 and d7. table 6 and the following subsections describe the functions of these bits. d7 and d6 each offer a method for determining whether a program or erase operation is complete or in progress. these three bits are discussed first. d7: /data polling the /data polling bit, d7, indicates to the host syst em whether an embedded algorithm is in progress or completed, or whether the device is in erase suspend. /data polling is valid after the rising edge of the final /we pulse in the program or erase command sequence. during the embedded program algorithm, the device outputs on d7 the complement of the datum programmed to d7. this d7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to d7. the system must provide the program address to read valid status information on d7. if a program address falls within a protected sector, /data polling on d7 is active for approximately 2 s, then the device returns to reading array data. during the embedded erase algorithm, /data polling produces a 0 on d7. when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, /data polling produces a 1 on d7. this is analogous to the complement/true datum output described for the embedded program algorithm: the erase function changes all the bits in a sector to 1; prior to this, the device outputs the complement, or 0. the system must provide an address within any of the sectors selected for erasure to read valid status information on d7. after an erase command sequence is written, if all sectors selected for erasing are protected, /data polling on d7 is active for approximately 100 s, then the device returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. when the system detects d7 has changed from the complement to true data, it can read valid data at d7~d0 on the following read cycles. this is because d7 may change asynchronously with d0~d6 while output enable (/oe) is asserted low. the /data polling timings (during embedded algorithms) figure in the ac characteristics section illustrates this. table 6 shows the outputs for /data polling on d7. figure 4 shows the /data polling algorithm.
issue 5.0 december 1999 page 24 d6: toggle bit i toggle bit i on d6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final /we pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cycles to any address cause d6 to toggle. (the system may use either /oe or /cs to control the read cycles.) when the operation is complete, d6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, d6 toggles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use d6 and d2 together to determine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), d6 toggles. when the device enters the erase suspend mode, d6 stops toggling. however, the system must also use d2 to determine which sectors are erasing or erase-suspended. alternatively, the system can use d7 (see the subsection on d7: /data polling). if a program address falls within a protected sector, d6 toggles for approximately 2 s after the program command sequence is written, then returns to reading array data. d6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. the write operation status table shows the outputs for toggle bit i on d6. refer to figure 5 for the toggle bit algorithm, and to the toggle bit timings figure in the ac characteristics section for the timing diagram. the d2 vs. d6 figure shows the differences between d2 and d6 in graphical form. see also the subsection on d2: toggle bit ii d2: toggle bit ii the toggle bit ii on d2, when used with d6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final /we pulse in the command sequence. d2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either /oe or /cs to control the read cycles.) but d2 cannot distinguish whether the sector is actively erasing or is erase-suspended. d6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information.
issue 5.0 december 1999 page 25 refer to table 6 to compare outputs for d2 and d6. figure 5 shows the toggle bit algorithm in flowchart form, and the section d2: toggle bit ii explains the algorithm. see also the d6: toggle bit i subsection. refer to the toggle bit timings figure for the toggle bit timing diagram. the d2 vs. d6 figure shows the differences between d2 and d6 in graphical form. reading toggle bits d6/d2 refer to figure 5 for the following discussion. whenever the system initially begins reading toggle bit status, it must read d7~d0 at least twice in a row to determine whether a toggle bit is toggling. typically, a system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on d7~d0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of d5 is high (see the section on d5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped tog-gling just as d5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and d5 has not gone high. the system may continue to monitor the toggle bit and d5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 5). d5: exceeded timing limits d5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions d5 produces a 1. this is a failure condition that indicates the program or erase cycle was not successfully completed. the d5 failure condition may appear if the system tries to program a 1 to a location that is previously programmed to 0. only an erase operation can change a 0 back to a 1. under this condition, the device halts the operation, and when the operation has exceeded the timing limits, d5 produces a 1. under both these conditions, the system must issue the reset command to return the device to reading array data.
issue 5.0 december 1999 page 26 d3: sector erase timer after writing a sector erase command sequence, the system may read d3 to determine whether or not an erase operation has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. when the ti me-out is complete, d3 switches from 0 to 1. the system may ignore d3 if the system can guarantee that the time between additional sector erase commands will always be less than 50 s. see also the sector erase command sequence section. after the sector erase command sequence is written, the system should read the status on d7 (/data polling) or d6 (toggle bit i) to ensure the device has accepted the command sequence, and then read d3. if d3 is 1, the internally controlled erase cycle has begun; all further commands (other than erase suspend) are ignored until the erase operation is complete. if d3 is 0, the device will accept additional sector erase commands. to ensure the command has been accepted, the system software should check the status of d3 prior to and following each subsequent sector erase command. if d3 is high on the second status check, the last command might not have been accepted. table 6 shows the outputs for d3.
tables issue 5.0 december 1999 page 27 device bus operation operation cs# oe# we# reset# a0~a20 d0~d7 read l l h h a in d out write l h l h a in d in cmos standby v cc + 0.5v x x v cc + 0.5v x high z ttl standby h x x h x high z output disable l h h h x high z hardware reset x x x l x high z temporary sector unprotect. (1) x x x v id a in d in legend : l = logic low= v il , h = logic high = v ih , v id = 12.0 +0.5v, x = dont care, d in = data in, d out = data out, a in = address in notes : see the sections on the sector group protection and temporary sector unprotect, for more information table 1 : device bus operations autoselect codes (high voltage method) description /cs# /oe /we a20 ~ a18 a17 ~ a10 a9 a8 ~ a7 a6 a5 ~ a2 a1 a0 d7~d0 01h (protected) sector group protection verification l l h sector group address x v id x v il x v ih v il 00h (unprotected) table 3 : autoselect codes legend : l = logic low= v il , h = logic high = v ih , sa = sector address, x = dont care. table 4 : sector group addresses sector group addresses sector group a20 a19 a18 sectors sga0 0 0 0 sa0~sa3 sga1 0 0 1 sa4~sa7 sga2 0 1 0 sa8~sa11 sga3 0 1 1 sa12~sa15 sga4 1 0 0 sa16~sa19 sga5 1 0 1 sa20~sa23 sga6 1 1 0 sa24~sa27 sga7 1 1 1 sa28~sa31
issue 5.0 december 1999 page 28 sector a20 a19 a18 a17 a16 address range sa0 0 0 0 0 0 000000h~00ffffh sa1 0 0 0 0 1 010000h~01ffffh sa2 0 0 0 1 0 020000h~02ffffh sa3 0 0 0 1 1 030000h~03ffffh sa4 0 0 1 0 0 040000h~04ffffh sa5 0 0 1 0 1 050000h~05ffffh sa6 0 0 1 1 0 060000h~06ffffh sa7 0 0 1 1 1 070000h~07ffffh sa8 0 1 0 0 0 080000h~08ffffh sa9 0 1 0 0 1 090000h~09ffffh sa10 0 1 0 1 0 0a0000h~0affffh sa11 0 1 0 1 1 0b0000h~0bffffh sa12 0 1 1 0 0 0c0000h~0cffffh sa13 0 1 1 0 1 0d0000h~0dffffh sa14 0 1 1 1 0 0e0000h~0effffh sa15 0 1 1 1 1 0f0000h~0fffffh sa16 1 0 0 0 0 100000h~10ffffh sa17 1 0 0 0 1 110000h~11ffffh sa18 1 0 0 1 0 120000h~12ffffh sa19 1 0 0 1 1 130000h~13ffffh sa20 1 0 1 0 0 140000h~14ffffh sa21 1 0 1 0 1 150000h~15ffffh sa22 1 0 1 1 0 160000h~16ffffh sa23 1 0 1 1 1 170000h~17ffffh sa24 1 1 0 0 0 180000h~18ffffh sa25 1 1 0 0 1 190000h~19ffffh sa26 1 1 0 1 0 1a0000h~1affffh sa27 1 1 0 1 1 1b0000h~1bffffh sa28 1 1 1 0 0 1c0000h~1cffffh sa29 1 1 1 0 1 1d0000h~1dffffh sa30 1 1 1 1 0 1e0000h~1effffh sa31 1 1 1 1 1 1f0000h~1fffffh table 2 : sector address table note : all sectors are 64kbyte in size.
issue 5.0 december 1999 page 29 bus cycles (2~4) first second third fourth fifth sixth command sequence (1) cycles addr data addr data addr data addr data addr data addr data read (5) 1 ra rd reset (6) 1 xxx f0 xx00 autoselect (7) sgp verify (8) 4 555 aa 2aa 55 555 90 sga x02 xx01 program 4 555 aa 2aa 55 555 a0 pa pd chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspend (9) 1 xxx b0 erase resume (10) 1 xxx 30 table 5 : command definitions legend: x = dont care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the /we or /cs# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of /we or /cs# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a20Ca16 select a unique sector. sga = address of the sector group to be verified. address bits a20Ca18 select a unique sector group. sgp = sector group protect. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except when reading array or autoselect data, all bus cycles are write operations. 4. address bits a20Ca11 are dont cares for unlock and command cycles, unless sa or pa required. 5. no unlock or command cycles required when reading array data. 6. the reset command is required to return to reading array data when device is in the autoselect mode, or if d5 goes high (while the device is providing status data). 7. the fourth cycle of the autoselect command sequence is a read cycle. 8. the data is 00h for an unprotected sector group and 01h for a protected sector group.see autoselect command sequence for more information. 9. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 10. the erase resume command is valid only during the erase suspend mode.
issue 5.0 december 1999 page 30 operation d7 (1) d6 d5 (2) d3 d2 (1) ry/by# embedded program algorithm d7# toggle 0 n/a no toggle 0 standard mode embedded erase algorithm 0 toggle 0 1 toggle 0 reading within erase suspended sector 1 no toggle 0 n/a toggle 1 reading within non-erase suspended sector data data data data data 1 erase suspend mode erase-suspend-program d7# toggle 0 n/a n/a 0 table 6 : write operation status notes: 1. d7 and d2 require a valid address when reading status information. refer to the appropriate subsection for further details. 2. d5 switches to 1 when an embedded program or embedded erase operation has exceeded the maximum timing limits. see d5: exceeded timing limits for more information.
package details page 31 issue 5.0 december 1999 puma 68 pin jedec surface mounted plcc 25.02 (0.985) 0.90 (0.035) typ 23.11 (0.910) 5.08 (0.200) max 24.13 (0.950) 25.27 (0.995) 1.27 (0.050) 0.46 (0.018) pin 68 pin 1
customer guidelines page 32 issue 5.0 december 1999 co planarity specified as +/- 2 thou max. visual inspection standard all devices inspected to ansi 2 standard moisture sensitivity devices are moisture sensitive. shelf life in sealed bag 12 months at <40 o c and <90% relative humidity (rh). after this bag has been opened, devices that will be subjected to infrared reflow, vapour phase reflow, or equivalent processing (peak package body temp 220 o c) must be : a : mounted within 72 hours at factory conditions of <30 o c/60% rh or b : stored at <20% rh if these conditions are not met or indicator card is >20% when read at 23 o c +/-5% devices require baking as specified below. if baking is required, devices may be baked for :- a : 24 hours at 125 o c +/-5% for high temperature device containers or b : 192 hours at 40 o c +5 o c/-0 o c and <5% rh for low temperature device containers . packaging standard devices packaged in dry nitrogen, jed-std-020. packaged in trays as standard. tape and reel available for shipment quantities exceeding 200pcs upon request. soldering recomendations ir/convection - ramp rate 6 o c/sec max. temp. exceeding 183 o c 150 secs. max. peak temperature 225 o c time within 5 o c of peak 20 secs max. ramp down 6 o c/sec max. vapour phase - ramp up rate 6 o c/sec max. peak temperature 215 - 219 o c time within 5 o c of peak 60 secs max. ramp down 6 o c/sec max. note : the above recomendations are based on standard industry practice. failiure to comply with the above recomendations invalidates product warranty.
ordering information page 33 issue 5.0 december 1999 http://www.mosaicsemi.com/ ordering information note : although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. our products are subject to a constant process of development. data may be changed without notice. products are not authorised for use as critical components in life support devices without the express written approval of a company director. puma 68f64006x i - 90 speed 90 = 90ns 120 = 120ns 150 = 150ns temp. range/screening blank = commercial i = industrial power consumption blank = standard pinout configuration x = industry standard pinout memory organisation 64006 = configurable as 8m x 8, 4m x 16 or 2m x 32 technology f = flash package puma 68 = 68 pin j leaded plcc http://www.mosaicsemi.com/

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